The present invention relates to a semiconductor integrated circuit device in which an I/O cell can be disposed in a desired position within a chip, a design method for the same and a computer-readable recording medium in which an I/O cell library is recorded.
Recently, a development to build a whole system on one chip, namely, a system on chip technique, has been advanced. As a result, in accordance with increase in scale of semiconductor integrated circuits, the number of pins included in a semiconductor integrated circuit tends to increase.
In order to cope with the increased number of pins, a semiconductor integrated circuit device using bumps arranged in the form of a matrix within a chip, namely, area bumps, has been proposed. Furthermore, as a result of the appearance of the area bumps, a technique to provide I/O cells to be connected to the area bumps in desired positions within the chip has been proposed.
Now, a conventional semiconductor integrated circuit device having an area bump structure disclosed in Japanese Laid-Open Patent Publication No. 5-218204 will be described with reference to FIG. 13. Herein, an internal circuit cell means a basic cell in a gate array type semiconductor integrated circuit and a standard cell in a standard cell type semiconductor integrated circuit.
As is shown in FIG. 13, bumps (area bumps) 11 are arranged in the form of a matrix within a chip 10, and an I/O cell 12 is disposed below each bump 11 in the chip 10 so as to be inserted between cell lines 13 corresponding to lines of internal circuit cells (not shown), namely, so as to be buried between the internal circuit cells.
Furthermore, an internal circuit cell region RCELL where the internal circuit cells are arranged extends over the entire chip 10.
In the semiconductor integrated circuit device using the area bumps, however, since the I/O cells are inserted in the internal circuit cell region, the area of the internal circuit cell region is increased, which increases the total line length of inter-cell wires (wires for connecting the internal circuit cells to each other and wires for connecting the internal circuit cells to the I/O cells). Therefore, propagation delay time of signals is increased in the entire semiconductor integrated circuit (LSI), which causes a problem of a low operation speed of the LSI.
In consideration of the aforementioned conventional problem, an object of the invention is, in a semiconductor integrated circuit device in which an I/O cell can be disposed in a desired position within a chip, reducing the total line length of inter-cell wires by reducing the area of an internal circuit cell region.
In order to achieve the object, the present inventors have examined the layout of I/O cells.
Now, conventional I/O cells will be described with reference to FIGS. 14 and 15.
FIG. 14 is a schematic diagram for showing the layout of a conventional input I/O cell (hereinafter referred to as the input cell).
As is shown in FIG. 14, the input cell 12a includes a first partial circuit 21 composed of an input buffer and a logic circuit, an input ESD (electrostatic discharge) protection circuit 22 and an input pad 23. The input pad 23 is connected to a corresponding bump 11 by soldering or the like.
FIG. 15 is a schematic diagram for showing the layout of a conventional output I/O cell (hereinafter referred to as the output cell).
As is shown in FIG. 15, the output cell 12b includes a second partial circuit 24 composed of an output pre-buffer and a logic circuit, an output ESD protection circuit 25 and an output pad 26. The output pad 26 is connected to a corresponding bump 11, by soldering or the like.
The output cell 12b is different from the input cell 12a in the output ESD protection circuit 25 including an output buffer/ESD protection circuit 25a working also as an output buffer and an ESD protection dedicated circuit 25b not working as the output buffer.
ESD is a phenomenon that an LSI is damaged by momentary flow of a large current (surge current) derived from static electricity caused when the LSI is touched by a man during wafer fabrication or the like. Therefore, the ESD protection circuit is characterized by use of a transistor having a much larger size than a transistor used in the internal circuit cell so as to withstand a large current exceeding 1 A. Accordingly, the ESD protection circuit occupies the most of the area of the I/O cell.
The circuit is typically not powered during ESD events. Under normal operating condition, i.e., when the chip is powered up, the input ESD protection circuit 22 and the ESD protection dedicated circuit 25b do not affect the operation of the LSI and the output buffer/ESD protection circuit 25a works as the output buffer alone.
The output buffer/ESD protection circuit 25a transfers a signal of the chip 10 through the bump 11 to the outside of the chip 10, and hence, the output buffer/ESD protection circuit 25a is required to have large driving power. Also, when a distance between the output buffer/ESD protection circuit 25a and the bump 11 is large, a signal transfer rate between the bump 11 and the output cell 12b is lowered, and therefore, the distance between the output buffer/ESD protection circuit 25a and the bump 11 should be as small as possible.
The present invention was devised on the basis of the aforementioned findings, and specifically, the semiconductor integrated circuit device of this invention in which at least one I/O cell is able to be disposed in a desired position within a chip, comprises an ESD protection circuit separated from the I/O cell and disposed in an ESD protection circuit region provided in a peripheral portion of the chip; the I/O cell disposed closer to a center of the chip than the ESD protection circuit region; and a wire for connecting the I/O cell to the ESD protection circuit.
In the present semiconductor integrated circuit device, the ESD protection circuit that occupies the most of the area of a conventional I/O cell is separated from the I/O cell so as to be disposed in the ESD protection circuit region provided in the peripheral portion of the chip, and the I/O cell is disposed closer to the center of the chip than the ESD protection circuit region. Therefore, even when the I/O cell is inserted in an internal circuit cell region, the area of the internal circuit cell region can be reduced as compared with that in a conventional semiconductor integrated circuit device, resulting in reducing the total line length of inter-cell wires. Accordingly, propagation delay time of signals can be reduced in the entire LSI, resulting in realizing a high operation speed of the LSI.
In the semiconductor integrated circuit device, it is preferred that the I/O cell is an input cell or a power cell, and that the whole of the ESD protection circuit is separated from the I/O cell to be disposed in the ESD protection circuit region and is connected to the I/O cell through the wire.
In this manner, the area of the internal circuit cell region can be further reduced.
In the semiconductor integrated circuit device, it is preferred that the I/O cell is an output cell, and that an ESD protection dedicated circuit corresponding to a portion of the ESD protection circuit not working as an output buffer is separated from the I/O cell to be disposed in the ESD protection circuit region and is connected to the I/O cell through the wire.
In this manner, the area of the internal circuit cell region can be reduced without increasing signal transfer time between the I/O cell and a bump provided above the I/O cell.
The design method of this invention for a semiconductor integrated circuit device in which one or more I/O cells are able to be disposed in desired positions within a chip, comprises a first arrangement step of arranging the I/O cells and one or more internal circuit cells within the chip; a first wiring step of connecting the internal circuit cells arranged in the first arrangement step to each other or to the I/O cells through inter-cell wires; a second arrangement step of arranging one or more ESD protection circuits separated from the I/O cells in an ESD protection circuit region provided in a peripheral portion of the chip; and a second wiring step of connecting the I/O cells arranged in the first arrangement step to the ESD protection circuits arranged in the second arrangement step through ESD protection wires, and the I/O cells are disposed closer to a center of the chip than the ESD protection circuit region in the first arrangement step.
In the present design method for a semiconductor integrated circuit device, the ESD protection circuit that occupies the most of the area of a conventional I/O cell is separated from the I/O cell so as to be disposed in the ESD protection circuit region provided in the peripheral portion of the chip, and the I/O cell is disposed closer to the center of the chip than the ESD protection circuit region. Therefore, even when the I/O cell is inserted in an internal circuit cell region, the area of the internal circuit cell region can be reduced as compared with that in a conventional semiconductor integrated circuit device, so as to reduce the total line length of inter-cell wires. Accordingly, the propagation delay time of signals can be reduced in the entire LSI, resulting in realizing a high operation speed of the LSI.
Preferably, the design method for a semiconductor integrated circuit device further comprises, between the first wiring step and the second arrangement step, a layout abstraction step of drawing an inclusion line surrounding all of the I/O cells arranged in the first arrangement step and grating lines each extending between the I/O cells or between one of the I/O cells and the inclusion line, and defining a capacity of every grating line corresponding to the number of ESD protection wires permitted to cross the grating line; and an I/O cell allocation step of drawing, with respect to every I/O cell, an I/O cell allocation line extending between the I/O cell and a point on the inclusion line in a manner that the I/O cell allocation line does not cross another I/O cell allocation line and that the number of I/O cell allocation lines crossing every grating line does not exceed the capacity, and the ESD protection circuits are disposed in accordance with the order of the I/O cells each allocated to one point on the inclusion line by using the I/O cell allocation lines in the second arrangement step, and the ESD protection wires are provided in a single interconnection layer alone in the second wiring step.
In this manner, the ESD protection circuits separated from the I/O cells can be disposed so that the ESD protection wires can be provided on a single interconnection layer alone. Therefore, increase of the fabrication cost derived from increase of interconnection layers for providing the ESD protection wires can be avoided.
In the design method for a semiconductor integrated circuit device, it is preferred that the first wiring step includes a sub-step of providing, within the chip, a wire region where the inter-cell wires are disposed, that the design method further includes, between the first wiring step and the second arrangement step, a wire region detection step of detecting the wire region provided in the first wiring step, and that the second arrangement step includes a sub-step of disposing the ESD protection circuits in the wire region detected in the wire region detection step.
In this manner, the area of the ESD protection circuit region provided in the peripheral portion of the chip can be reduced, so as to reduce the area of the chip itself. As a result, the fabrication cost can be lowered and the yield can be improved.
In the computer-readable recording medium of this invention, an I/O cell library corresponding to a set of I/O cells for externally inputting a signal to or outputting a signal from a semiconductor integrated circuit is recorded, and the I/O cell library includes at least one ESD protection circuit separated from the I/O cells as a cell different from the I/O cells.
According to the present computer-readable recording medium, the design method for a semiconductor integrated circuit device of this invention can be easily practiced by utilizing the I/O cell library recorded in the recording medium on a computer.